Carbon nanotube memory will replace DRAM soon

Nantero described the new generation of non-volatile random access memory (NRAM) based on carbon nanotubes (CNT) at this year's Hot Chips conference and believed that it will become a future alternative to DRAM.

Nantero, an American supplier of random memory, announced its new generation of non-volatile random access memory (NRAM) designs based on carbon nanotubes (CNT) at Hot Chips this year, and believed that it will become a replacement for DRAM. Nantero's first step is to team up with industry partner Fujitsu, aiming to launch a DRAM alternative using the technology next year.

Currently, DRAM has the largest share of the semiconductor market, expected to surpass $100 billion in sales this year partly thanks to the spiking prices. However, DRAM is expected to encounter bottlenecks in 64Gbit components, driving industry vendors such as Micron to actively explore alternatives such as phase-change memory.

Nantero's non-volatile NRAM uses electrostatic charge to excite random arrays of CNT cells, which are said to be relatively easy to spin-coat on to any CMOS process. It claims that NRAM technology will surpass the DRAM roadmap by introducing a 100mm² wafer fabricated on a 28nm process and stacking 4Gbit CNT layers in 8Gb and 16Gb components.

Chief Architect for Nantero, Bill Gervasi said, "This is a good start - because it is a market in itself."

Theoretically, DDR4 can support up to 8 layers of stacking and DDR5 can handle up to 16 layers. What’s more, future processes may achieve denser individual layers. Nantero predicts a 64Gbit NRAM can be manufactured in a 14nm process, and a 256-Gbit component in 7nm, both using four layers of stacking.

Gervasi said that Nantero has created a DDR4 reference design to drive the development of NRAM technology, which is a scalable way beyond DRAM, and that they had a comfortable road map to replace DRAM.

During the post-meeting questioning process, participants tried to poke holes in the new technology approach but found no significant gaps. Gervasi said, "I have been waiting for the final result with great fear. We have already manufactured thousands of test chips, although not a 16Gbit component."

The CNT cell exhibits some variations from the standard DRAM timing. However, they should work with an unmodified DRAM controller and provide read/write speeds down to 5 nanoseconds (ns) and 5 femtojoules per bit (fj/bit) in the power envelop of DRAM DIMMs.

He said, "Customers will encrypt on the processor side" in response to the non-volatile nature of the main memory. He pointed out that efforts over the past several years have now provided support for non-volatile main memory in Windows, Linux and applications.

NRAM timing with ECC differs from DRAMs but it can still use existing controllers（Image：Nantero）

Regarding soft errors, he said, "These components have been put into space, and we can have data on temperature, alpha and gamma rays – there’s nothing you can do with a CNT to get it to do something weird."

Part of Nantero’s secret sauce is in the slurry used to form the CNTs and details of the components size and shape. “We design and manufacture equipment at the vendor’s site,” he said. The company also has proprietary technology on how to direct electrostatic signals for reading and writing.

Nantero announced in April it secured of $29.7 million from eight investors including DIMM-maker Kingston, Dell’s investment divisions Dell Technologies Capital, Cisco’s investment divisions Cisco Investments and SMIC’s investment divisions CFT Capital.

 (Reference text：Nantero Details DRAM Alternative，by Rick Merritt)