Encapsulation not only is the last step in chip manufacturing, but also provides a landing zone for the chip's electrical signals and power sources as the physical interface between the processor and the motherboard. As the electronics industry moves toward a data-centric era, packaging is becoming a catalyst for product innovation. Advanced packaging technologies can integrate computing engines with multiple process processes to achieve performance similar to a single chip, but their platform range far exceeds the chip size limitations of single chip integration. These technologies will greatly improve product-level performance and efficiency, shrink the area, and overhaul the system architecture.

At this week's SEMICON West conference in San Francisco, Intel unveiled a new set of basic tools opening a new dimension to chip architecture, which include the Co-EMIB(innovative applications combine EMIB with Foveros ), ODI (Omni-Directional Interconnect) and MDIO (new bare chip indirect port technology.)

Intel expects to use advanced technology to package chips and small chips together in order to achieve system-level performance on a single chip. Heterogeneous integration technology makes it possible to match various IP and process technologies with different memory and I/O units in new diversified modules. Intel's vertically integrated architecture optimizes architecture, process, and packaging.

Among them, EMIB (embedded multi-chip interconnection bridge) 2D packaging and Foveros 3D packaging technologies utilize high-density interconnection technology to achieve high bandwidth, low power consumption and competitive I/O density, while the Co-EMIB technology connects higher computational capabilities and capabilities. The Co-EMIB can interconnect two or more Foveros components to achieve basically single chip performance. Designers are also able to connect simulators, memory and other modules in very high bandwidth and very low power consumption.

At the same time, ODI provides greater flexibility for the Omni-directional interconnection communication between small and medium-sized packaged chips. The top chip can communicate horizontally with other small chips as in EMIB technology, and vertically with the bottom bare chip through a silicon through-hole (TSV) as in Foveros technology. The ODI uses large vertical through-holes to provide power directly to the top bare plate from the packaging substrate. The large through-holes are much larger than traditional silicon through-holes and have lower resistance, thus providing more stable power transmission, while achieving higher bandwidth and lower delay through stacking.

At the same time, this method reduces the number of silicon through-holes needed in the basal chip freeing up more area for active transistors and optimizes the size of bare chips. In addition, Intel has released a new bare chip indirect port technology called MDIO, which is based on its advanced interface bus (AIB) physical layer interconnection technology. MDIO technology supports the modular system design of small chip IP module library, which can provide higher energy efficiency and realize twice the response speed and bandwidth density more than that of AIB technology.

These new technologies expand Intel's toolbox and combine with Intel's process technologies to become creative palettes for chip architects, giving them the freedom to design innovative products.

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